Bridging the gap between software and silicon. Specializing in FPGA acceleration, custom bare-metal drivers, and real-time embedded systems.
I am a highly motivated Electronics and Communication Engineering student at Kangeyam Institute of Technology with a passion for designing high-performance digital circuits, bare-metal microcontroller drivers, and hardware-accelerated algorithms.
My approach combines hardware-software co-design using platforms like FPGAs (Vivado, Vitis HLS) and microcontrollers (STM32, MSP430) with rigorous low-level programming in Embedded C, Verilog, and SystemVerilog. I thrive at the interface where hardware architecture meets firmware logic.
I am actively seeking internships, co-ops, and full-time opportunities where I can apply my low-level development skills to build efficient, secure, and reliable embedded solutions.
Utilized custom architecture to map compute-intensive CNN operations (convolution, activation, pooling) onto FPGA hardware. Designed using HW/SW co-design with Vitis HLS and Vivado.
Developed an autonomous monitoring rover using Edge Impulse for custom dataset training. Features real-time COCO object detection and a video web server for disaster victim rescue operations.
Profiled and optimized deep learning architectures like AlexNet, ResNet, and MobileNet on the Xilinx ZCU104 FPGA. Achieved 25–45% power reductions compared to standard hardware platforms.
Simulated sinkhole attacks in wireless sensor networks using Cooja simulator and integrated the Twilio API to automatically dispatch real-time SMS alerts upon threat detection.
A custom, register-level STM32F103 (Blue Pill) driver library built from scratch in Embedded C. Features structured GPIO, timer, and register mappings designed to replace HAL overlays.
Open-source repository implementing CNN inference blocks on Xilinx ZCU104. Includes performance analyses and optimized deployment profiles for LeNet, MobileNetV2, and ResNet50.
Acquired hands-on industrial experience working with embedded firmware layers, designing digital logic interfaces, configuring custom microcontrollers, and exploring industrial automation protocols. Collaborated on hardware validation and debugging setup setups.
Currently pursuing B.E in ECE with a cumulative CGPA of 8.32 / 10 (Up to Semester V). Focus areas include VLSI Design, Microprocessor architectures, and Digital Signal Processing.
Graduated with a score of 87.33% in Core Sciences and Mathematics.
Completed secondary education with an All Pass distinction.
I believe in open-source development to share engineering tools, register configurations, and convolutional neural net deployments on FPGAs. Check out my key codebases:
Raw register configurations for GPIO, timers, and sysclock configs on Blue Pill.
Vivado synthesizable block layers for MobileNet, ResNet, and LeNet CNN engines.
Co-authored and presented a technical research paper on Dynamo Energy in E-Vehicles, proposing optimized regeneration feedback topologies.
Represented the college ECE department as a core firmware/backend developer in team 'Tech Wizards', creating IoT prototype endpoints.
Successfully completed the specialized Skill Development Program (SDP) in Cadence Virtuoso Analog Layout conducted by ICT Academy, mastering mask layout techniques.
Self-published an introductory guidebook on Amazon Kindle to help incoming university engineering freshmen and beginners build a strong foundation in raw, register-friendly C syntax.
Conducted technical training sessions on scientific software simulator platforms like GeoGebra and Google Earth. Introduced high-school students to open-source systems (BOSS Linux, LibreOffice).
Coordinated the planning, budgeting, and execution of department-level events. Managed outreach, scheduling, and communication between organizing student committees, participants, and college faculty.
I am seeking internships, co-ops, and full-time opportunities where I can apply my FPGA, VLSI, and firmware engineering skills to solve real-world hardware challenges.